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Diagram of a 4-bit DAC based on an R-2R Ladder
My understanding runs thus…
At the ‘bottom’ of the ladder, there’s a resistor of value 2R connected to ground. In parallel with this is another 2R, connected either to ground or to the output. going into point Y above, the resistance is therefore R (2 2R’s in parallel). At point X, the resistance is R + R as there are 2 R’s in series. 2 2R’s in parallel make another R, and the whole thing repeats.
In other words, the resistance on the way into any junction is always R (2 2R’s in parallel), and so theoretically the sequence could be extended to any number of bits, without ever requiring any resister values other than R and 2R. Obviously, there are physical limits to the number of bits you can have - things such as a restrictively high voltage that would be required to have a, say, 1024-bit R-2R Ladder working effectively (not to mention that it would be difficult to envisage a situation which requires this kind of resolution), but in theory such a DAC could be made without requiring any resistors other than R and 2R. That’s what I was alluding to before.
I’ll be glad of corrections! The concept doesn’t seem to translate to text very well, though - I’m not sure if any of the above quite made sense… :-)